HDL Works

HDL Works has released EASE 8.0

Most important new functionality in 8.0 is the virtual record. A virtual record is like a VHDL record in that it is a collection of signals, shown as a single signal object. Unlike a VHDL record, the virtual record will be expanded into the individual signals in the generated HDL. The virtual record type can be used as a port on an entity/module and as a port or wire in a diagram. The goal is to decrease the block diagram complexity and increase design flexibility.

On the right is an example of an entity with 83 ports. Using virtual records for groups like ddr2 and ethernet the visible amount of ports is only 32 ports

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EASE Virtual Record example

HDL Works

HDL Works is a supplier of front-end VHDL / Verilog design tools, translators and an FPGA / PCB pin assignment verification tool.
HDL Works has over 15 years experience developing HDL tools.

All tools are available on Windows and Linux operating systems.

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Design & Verification Products

EASE Graphical HDL Design tool.
Combines block diagrams, state diagrams, truth tables and HDL code.
HDL Companion The SWISS Army knife for every HDL Design Engineer
It will give you a complete overview of any VHDL or Verilog design in seconds.
Features include verification, linting and HTML generation.
IO Checker When using large FPGA's on a PCB making sure that the FPGA pins are connected to the right signals is a cumbersome task.
IO Checker uses rules (based on regular expressions) to match the signal names in both the FPGA and PCB design environment.
Scriptum A text editor focused at VHDL and Verilog, using a Multiple Document Interface.
(Free of charge)
ConnTrace ConnTrace is used to verify the connections between various PCB's, Independent on how your PCBs are connected (backplanes, connectors and/or rear panels). ConnTrace will present a view of the connections in seconds.

HDL Companion 2.6

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New: HDL Works has introduced
ConnTrace

Read more..ConnTrace 1.1
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IO Checker 2.2

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Translation products and services

FLDL2HDL Fujitsu FLDL netlist and FTDL test format translated into a VHDL or Verilog netlist.
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