HDL Works

HDL Works is a supplier of front-end VHDL / Verilog design tools, translators and an FPGA / PCB pin assignment verification tool.
HDL Works has over 15 years experience developing HDL tools.

All tools are available on Windows, Linux and Solaris operating systems.


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Design & Verification Products

EASE Graphical HDL Design tool.
Combines block diagrams, state diagrams, truth tables and HDL code.
HDL Companion The SWISS Army knife for every HDL Design Engineer
It will give you a complete overview of any VHDL or Verilog design in seconds.
Features include verification, linting and HTML generation.
IO Checker FPGA versus PCB pin assignment verification.
IO Checker uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment.
Scriptum A text editor focused at VHDL and Verilog, using a Multiple Document Interface.
(Free of charge)

New: IO Checker !!!

Verifying hundreds of FPGA pins in minutes IO Checker overview

Translation products and services

AHDL2HDL Altera AHDL language translator to VHDL and Verilog.
FLDL2HDL Fujitsu FLDL netlist and FTDL test format translated into a VHDL or Verilog netlist.
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