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    1  ////////////////////////////////////////////////////////////////////////////////
    2  //
    3  // This Verilog file was generated by EASE/HDL 7.0 1 from HDL Works B.V.
    4  //
    5  // Ease library  : work
    6  // HDL library   : work
    7  // Host name     : Dallas
    8  // User name     : willem
    9  // Time stamp    : Fri Dec 01 11:25:51 2006
   10  //
   11  // Designed by   : 
   12  // Company       : HDL Works
   13  // Project info  : 
   14  //
   15  ////////////////////////////////////////////////////////////////////////////////
   16  
   17  
   18  `include "work_defines.v"
   19  
   20  ////////////////////////////////////////////////////////////////////////////////
   21  // Object        : Module work.Slave_Pld_Bus2
   22  // Last modified : Wed Oct 11 11:46:19 2006.
   23  ////////////////////////////////////////////////////////////////////////////////
   24  
   25  module Slave_Pld_Bus2 (HADDR_pld_bus2, HBURST_pld_bus2, HCLK, HRDATA_slave7, 
   26    HRDATA_slave8, HRDATA_slave9, HREADY_IN_pld_bus2, HREADY_slave7, 
   27    HREADY_slave8, HREADY_slave9, HRESETn, HRESP_slave7, HRESP_slave8, 
   28    HRESP_slave9, HSEL, HSIZE_pld_bus2, HTRANS_pld_bus2, HWDATA_pld_bus2, 
   29    HWRITE_pld_bus2) ;
   30    input     [31:0]HADDR_pld_bus2;
   31    input     [2:0]HBURST_pld_bus2;
   32    input     HCLK;
   33    output    [31:0]HRDATA_slave7;
   34    output    [31:0]HRDATA_slave8;
   35    output    [31:0]HRDATA_slave9;
   36    input     HREADY_IN_pld_bus2;
   37    output    HREADY_slave7;
   38    output    HREADY_slave8;
   39    output    HREADY_slave9;
   40    input     HRESETn;
   41    output    [1:0]HRESP_slave7;
   42    output    [1:0]HRESP_slave8;
   43    output    [1:0]HRESP_slave9;
   44    input     [6:0]HSEL;
   45    input     [2:0]HSIZE_pld_bus2;
   46    input     [1:0]HTRANS_pld_bus2;
   47    input     [31:0]HWDATA_pld_bus2;
   48    input     HWRITE_pld_bus2;
   49  
   50  
   51    wire HCLOCK;
   52    wire clock_en;
   53    wire reg_write;
   54    wire [31:0]reg_wdata;
   55    wire [31:0]Net_11;
   56    wire [31:0]reg_wdata0;
   57    wire [31:0]Net_13;
   58    wire reg_write0;
   59    wire clock_en0;
   60    wire [63:0]Net_15;
   61    wire [31:0]Net_16;
   62    wire reg_write2;
   63    wire clock_en2;
   64    wire [63:0]reg_rdata;
   65    wire [31:0]rdata;
   66    wire [31:0]rdata0;
   67  
   68    assign HCLOCK = HCLK;
   69  
   70    single_transaction_slave
   71      Slave7(
   72        .HADDRESS(HADDR_pld_bus2),
   73        .HBURST(HBURST_pld_bus2),
   74        .HCLOCK(HCLOCK),
   75        .HRDATA(HRDATA_slave7),
   76        .HREADY(HREADY_slave7),
   77        .HRESETn(HRESETn),
   78        .HRESP(HRESP_slave7),
   79        .HSEL(HSEL[4]),
   80        .HSIZE(HSIZE_pld_bus2),
   81        .HTRANS(HTRANS_pld_bus2),
   82        .HWDATA(HWDATA_pld_bus2),
   83        .HWRITE(HWRITE_pld_bus2),
   84        .clock_en(clock_en),
   85        .reg_address(Net_11),
   86        .reg_rdata(rdata0),
   87        .reg_wdata(reg_wdata),
   88        .reg_write(reg_write),
   89        .wait_sig(1'b1) ) ;
   90  
   91    burst_slave
   92      Slave8(
   93        .HADDRESS(HADDR_pld_bus2),
   94        .HBURST(HBURST_pld_bus2),
   95        .HCLOCK(HCLOCK),
   96        .HRDATA(HRDATA_slave8),
   97        .HREADY(HREADY_slave8),
   98        .HRESETn(HRESETn),
   99        .HRESP(HRESP_slave8),
  100        .HSEL(HSEL[5]),
  101        .HSIZE(HSIZE_pld_bus2),
  102        .HTRANS(HTRANS_pld_bus2),
  103        .HWDATA(HWDATA_pld_bus2),
  104        .HWRITE(HWRITE_pld_bus2),
  105        .clock_en(clock_en0),
  106        .reg_address(Net_13),
  107        .reg_rdata(rdata),
  108        .reg_wdata(reg_wdata0),
  109        .reg_write(reg_write0),
  110        .wait_sig(1'b1) ) ;
  111  
  112    wide_slave #(3'b000, 3'b010, 3'b011, 3'b001, 3'b100)
  113      Slave9(
  114        .HADDRESS(HADDR_pld_bus2),
  115        .HBURST(HBURST_pld_bus2),
  116        .HCLOCK(HCLOCK),
  117        .HRDATA(HRDATA_slave9),
  118        .HREADY(HREADY_slave9),
  119        .HREADY_in(HREADY_IN_pld_bus2),
  120        .HRESETn(HRESETn),
  121        .HRESP(HRESP_slave9),
  122        .HSEL(HSEL[6]),
  123        .HSIZE(HSIZE_pld_bus2),
  124        .HTRANS(HTRANS_pld_bus2),
  125        .HWDATA(HWDATA_pld_bus2),
  126        .HWRITE(HWRITE_pld_bus2),
  127        .clock_en(clock_en2),
  128        .reg_address(Net_16),
  129        .reg_rdata(reg_rdata),
  130        .reg_wdata(Net_15),
  131        .reg_write(reg_write2),
  132        .wait_sig(1'b1) ) ;
  133  
  134    regfile
  135      Slave7_regfile(
  136        .address(Net_11[6:2]),
  137        .clock(HCLOCK),
  138        .clock_en(clock_en),
  139        .rdata(rdata0),
  140        .reset(HRESETn),
  141        .wdata(reg_wdata),
  142        .write(reg_write) ) ;
  143  
  144    regfile
  145      Slave8_regfile(
  146        .address(Net_13[6:2]),
  147        .clock(HCLOCK),
  148        .clock_en(clock_en0),
  149        .rdata(rdata),
  150        .reset(HRESETn),
  151        .wdata(reg_wdata0),
  152        .write(reg_write0) ) ;
  153  
  154    regfile
  155      Slave9_regfile_high(
  156        .address(Net_16[7:3]),
  157        .clock(HCLOCK),
  158        .clock_en(clock_en2),
  159        .rdata(reg_rdata[63:32]),
  160        .reset(HRESETn),
  161        .wdata(Net_15[63:32]),
  162        .write(reg_write2) ) ;
  163  
  164    regfile
  165      Slave9_regfile_low(
  166        .address(Net_16[7:3]),
  167        .clock(HCLOCK),
  168        .clock_en(clock_en2),
  169        .rdata(reg_rdata[31:0]),
  170        .reset(HRESETn),
  171        .wdata(Net_15[31:0]),
  172        .write(reg_write2) ) ;
  173  
  174  endmodule // Slave_Pld_Bus2(structure)
  175  
  176
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