1  --------------------------------------------------------------------------------
    2  --
    3  -- This VHDL file was generated by EASE/HDL 7.0 from HDL Works B.V.
    4  --
    5  -- Ease library  : uart
    6  -- HDL library   : uart
    7  -- Host name     : Dallas
    8  -- User name     : willem
    9  -- Time stamp    : Fri Dec 01 11:40:03 2006
   10  --
   11  -- Designed by   : www.opencores.org
   12  -- Company       : HDL Works
   13  -- Project info  : This core adheres to the GNU public license
   14  --
   15  --------------------------------------------------------------------------------
   16  
   17  --------------------------------------------------------------------------------
   18  -- Object        : Entity uart.TxTransmit
   19  -- Last modified : Fri Dec 01 11:39:52 2006.
   20  --------------------------------------------------------------------------------
   21  
   22  
   23  library ieee;
   24  use ieee.std_logic_1164.all;
   25  use ieee.numeric_std.all;
   26  use ieee.std_logic_unsigned.all;
   27  
   28  entity TxTransmit is
   29    port(
   30      Clk      : in     std_logic;
   31      Reset    : in     std_logic;
   32      TBufE    : in     std_logic;
   33      TBufF    : in     std_logic_vector(7 downto 0);
   34      TRegE    : out    std_logic;
   35      TxBdEdge : in     std_logic;
   36      TxDat    : out    std_logic;
   37      WdFmt    : in     std_logic_vector(2 downto 0));
   38  
   39  end entity TxTransmit ;
   40  
   41  --------------------------------------------------------------------------------
   42  -- Object        : Architecture uart.TxTransmit.fsm
   43  -- Last modified : Fri Dec 01 11:39:52 2006.
   44  --------------------------------------------------------------------------------
   45  architecture fsm of TxTransmit is
   46  
   47  -- State Machine Options:
   48  --  Clock : Clk (Falling edge).
   49  --  Clock enable : TxBdEdge (High).
   50  --  State assignment : Enumerate.
   51  --  State decoding : Case construct.
   52  --  Actions on transitions : Clocked.
   53  --  Actions on states : Clocked.
   54    type state_type is (Idle, Start, Data, Parity, Stop) ;
   55    signal state : state_type  ;  -- Current State
   56  
   57  signal TReg : std_logic_vector(7 downto 0);
   58  signal TxParity : std_logic;
   59  signal DataCnt : std_logic_vector(3 downto 0);
   60  signal TxDbit : std_logic;
   61  
   62  begin
   63    TxDat <= TxDbit;
   64  
   65  
   66    state_decoding: process (Clk, Reset) is
   67    begin
   68      if (Reset = '1') then
   69        state <= Idle ;
   70        -- rst:
   71          TxDbit   <= '1';
   72          TReg     <= "00000000";
   73          TxParity <= '0';
   74          DataCnt  <= "0000";
   75          TRegE    <= '1';
   76      elsif (Clk'event and (Clk = '0')) then
   77        if (TxBdEdge = '1') then --  Clock enable
   78          case state is
   79            when Idle =>
   80              if (TBufE = '0') then
   81                state <= Start ;
   82                -- start:
   83                  TxDbit    <= '0';
   84                  TReg      <= TReg;
   85                  TxParity  <= '0';
   86                  if WdFmt(2) = '0' then
   87                    DataCnt <= "0110";  -- 7 data + parity
   88                  else
   89                    DataCnt <= "0111";  -- 8 data
   90                  end if;
   91                  TRegE     <= '0';
   92              end if ;
   93            when Start =>
   94                state <= Data ;
   95                -- data:
   96                  TxDbit   <= TReg(0);
   97                  TReg     <= '1' & TReg(7 downto 1);
   98                  TxParity <= TxParity xor TReg(0);
   99                  DataCnt  <= DataCnt - "0001";
  100                  TRegE    <= '0';
  101            when Data =>
  102              if (
  103                DataCnt = "0000" and 
  104                WdFmt(2 downto 1) = "10" and 
  105                WdFmt(0) = '0'
  106                ) then
  107                state <= Stop ;
  108                -- stop:
  109                  TxDbit   <= '1';  -- 2 stop bits
  110                  TReg     <= TReg;
  111                  TxParity <= '0';
  112                  DataCnt  <= "0000";
  113                  TRegE    <= '0';
  114              elsif (
  115                DataCnt = "0000" and 
  116                WdFmt(2 downto 1) = "10"
  117                ) then
  118                state <= Idle ;
  119                -- idle:
  120                  TxDbit   <= '1';
  121                  TReg     <= TBufF;
  122                  TxParity <= '0';
  123                  DataCnt  <= "0000";
  124                  TRegE    <= '1';
  125              elsif (
  126                DataCnt = "0000" and 
  127                WdFmt(2 downto 1) /= "10"
  128                ) then
  129                state <= Parity ;
  130                -- parity:
  131                  if WdFmt(0) = '0' then
  132                    TxDbit <= not(TxParity);  -- even parity
  133                  else
  134                    TxDbit <= TxParity;       -- odd parity
  135                  end if;
  136                  TReg     <= TReg;
  137                  TxParity <= '0';
  138                  DataCnt  <= "0000";
  139                  TRegE    <= '0';
  140              end if ;
  141            when Parity =>
  142              if (WdFmt(1) = '0') then
  143                state <= Stop ;
  144                -- stop:
  145                  TxDbit   <= '1';  -- 2 stop bits
  146                  TReg     <= TReg;
  147                  TxParity <= '0';
  148                  DataCnt  <= "0000";
  149                  TRegE    <= '0';
  150              else
  151                state <= Idle ;
  152                -- idle:
  153                  TxDbit   <= '1';
  154                  TReg     <= TBufF;
  155                  TxParity <= '0';
  156                  DataCnt  <= "0000";
  157                  TRegE    <= '1';
  158              end if ;
  159            when Stop =>
  160                state <= Idle ;
  161                -- idle:
  162                  TxDbit   <= '1';
  163                  TReg     <= TBufF;
  164                  TxParity <= '0';
  165                  DataCnt  <= "0000";
  166                  TRegE    <= '1';
  167            when others =>   --REST state
  168                state <= Idle ;
  169                -- idle:
  170                  TxDbit   <= '1';
  171                  TReg     <= TBufF;
  172                  TxParity <= '0';
  173                  DataCnt  <= "0000";
  174                  TRegE    <= '1';
  175              assert false
  176                report "REST state executed"
  177                severity Warning ;
  178          end case ;
  179        end if ; -- Clock enable
  180      end if ; --  Reset & Clock
  181    end process state_decoding ;
  182  
  183  end architecture fsm ; -- of TxTransmit
  184  
  185