What's new in EASE™ 7.4
We are pleased with all the new features in EASE 7.4.
To give you an impression we have listed the most important
changes below.
New functionality:
- Master/Slave state machine support
- Push Down Re-Factoring
- Support for corporate data
- $CORPORATE/hdlworks/ease/etc/ease.xml : corporate profile
- $CORPORATE/hdlworks/etc/etc/packages.xml : corporate packages
- External files/documents can be added to entity/modules/architecture to document the object.
- VHDL architectures can be implemented in an external HDL file.
- Added an Example Projects sub menu to the File menu.
- VHDL-2008 support:
- Automatic sensitivity list for process
- Verilog 2001 support:
- Automatic event list for process
- Support for Xilinx ISim HDL Simulator
Improvements & bug fixes:
- Performance: loading, closing and generating HDL has been improved a lot for projects that are located on a network drive. For networked projects improvements up to 80% have been realized.
- Improved Verilog import of (simple) generate statements.
- Select the object representing the level we came from after level up in one of the editors
- Verify/Lint/Hdl Generate for selected library object in the database view.
- Included Text 'Declarations after Components', can be used to define attributes on components.
- Import of multiple libraries from another Ease project
- Display label text for virtual transitions.
- Allow VHDL direct instantiation of an entity.
- Improved Entity/Module properties dialogue.
- Allow slice or index definition for a connection to be defined with Connect By Name dialogue.
- Added centring of all objects in a schematic.
- Clock enable in an FSM can be specified as an expression.
- Startup state of a state machine can be explicitly set.
- Placed pragma around library statements only used with use clause that have pragmas
Scriptum:
- Improved type assistant by adding 2 configurations options (minimum characters typed and match only words from the start).
- Added a dialog to options menu to change file associations.
- Text folding for VHDL and Verilog files.
- Color schemes can be assigned to a language.
- Dialog to create of modify color schemes.
- Allow <ALT><mouse> for column selections, besides <cntrl> key.
- Keyboard accelerator for exit is now CTRL+Q (was ALT+X)
- Changed all keyboard accelerators for dropping bookmarks from <alt><ctrl><0-9> into <alt><0-9> to recognize the German <Alt-Gr> key for special characters.
- Option to retain undo/redo stack after save.
 More about EASE
EASE 7.4 Release Notes
Download EASE 7.4 now:
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