Exploring IO Checker

Signal View The Signal View shows the information extracted from the FPGA and PCB data. It shows for each device pad number, bank number, the FPGA signal name, PCB signal name and when available the constraint signal name and I/O type. It shows also voltage errors and warnings. You can organize the Signal View using the several sort options and filters so you can concentrate on the potential mismatches.

HDL View

The HDL View is only visible when a VHDL or Verilog file has been added to the project. The view shows all toplevel ports and shows to which pad they have been assigned if this information is available. You can use this view to assign the ports to a pad in the Signal View to create or update a constraint file. You can filter already assigned ports to concentrate on the unassigned ports only.

Device View The Device View provides a graphical representation of the FPGA package footprint. It shows the I/O banks, differential pin pairs and special pins, like power/ground and control pins. HDL signals can be assigned in the Device View to create or update a constraint file. The pins in the Device View can be hidden depending on various criteria like unused on the PCB, power/ground, control pins, etc. The view can help you to optimize the pin assignment for critical high speed signals.

Matching Rules

IO Checker uses rules (based on regular expressions) to match the signal names in both the FPGA and PCB design environment. It allows the tool to validate groups of matches although individual signals can still differ. The rules can be generated automatically by the Rule Generator or manually by the user. IO Checker uses also fuzzy matching rules for common differences between the FPGA and PCB signal names, for example bus indexes. The automated rules approach will often match 80% to 90% of all device pins.

Power and Ground verification

Another mistake sometimes made is related to the power pins. The FPGA IO banks can require a different voltage than the FPGA core voltage and these banks can be programmed for different IO standards requiring a different voltage supply. IO Checker extracts the required power information from the FPGA pin file and device information and compares it with the voltage information from the PCB netlist. The power verification results are shown in the Verification Window. The results are hot-linked to the corresponding pad number in the Signal View. An icon in the Signal View denotes also the power status.

HTML Report Generator

IO Checker can create an HTML report of your project including:

• Summary
• Rules report
• Signal View sorted by severity
• Signal View sorted by pad number
• Verification results