What's new in IO Checker™ 2.1

Intelligent power extraction from decoupled power supplies

IO Checker can now recognize secondary power nets which feed (analog) power pins of an FPGA and are connected through a decoupling circuit (inductor and capacitors to GND) to the main power supplies on the PCB. A warning message is generated when decoupled power nets indicate different voltage strength.

Extended signal name extraction

Additional signal information is shown in the PCB column for nets that are decoupled with a single resistor.

Automatic PCB netlist format recognition

IO Checker can automatically determine the format of the netlist specified based on the file extension and known keywords that are found in the file.

Company corporate data directory and settings

Company global settings like used FPGA vendor, PCB vendor and default matching rules can be defined and stored on a directory that each designer can use to retrieve the standard settings.

Tooltips on PCB signal names

A tooltip with all connected pins of the associated net will be shown when the tooltip is activated in the PCB signal column.

User accepted power mismatches

The designer can manually accept a power mismatch and mark as correct. The error flag will be replaced by a user accepted flag. The user accepted flag will be removed when the design data is re-importing with different power values.

Device Support

• Actel
• SmartFusion
• Altera
• Cyclone IV E
• Stratix V
• Xilinx
• Kintex-7
• Virtex-7

Extended Device Support

• Altera
• Arria V
• Cyclone V
• Stratix V
• Xilinx
• Artix-7
• Kintex-7
• Virtex-7

Download IO Checker 2.1 now:

• Software (including manual)