| 1366 |
Backup file restore |
7.4.8 |
Single backup file are not correctly restored |
| 1364 |
Incomplete label in browser for instance inside HDL file architecture |
7.4.8 |
Label for fuzzy instance does not show referred entity if a direct instantiation is used. |
| 1363 |
Not all files generated when hierarchy inside HDL file architecture |
7.4.8 |
In some cases hierarchy inside an architecture HDL file is not taken into
account when generating code hierarchically. |
| 1355 |
HDL files are opened in write mode while project is readonly. |
7.4.8 |
Occurs when navigation through the hot errors. |
| 1344 |
USB Dongle issue |
7.4.7 |
On 64-bit Windows only the first USB dongle is detected |
| 1338 |
CBN tags not updated |
7.4.7 |
CBN tags are not update when only the net constraint is changed |
| 1334 |
Allow integer range. |
7.4.7 |
Allow integer range specification in the port/generic/declaration dialogs |
| 1320 |
Diagram editor font change has delayed effect |
7.4.7 |
Changing diagram editor font name in user settings only works after restarting Ease |
| 1318 |
VHDL 2008: floating point packages not supported |
7.4.7 |
The VHDL 2008 packages ieee.fixed_float_types_c, ieee.fixed_pkg_c and
ieee.float_pkg_c are not supported when VHDL 2008 is selected as VHDL version.
The packages are compiled in the library ieee_proposed. |
| 1315 |
HDL update incorrect |
7.4.7 |
Dependencies were not updated after entity name changes |
| 1314 |
Port push-up dialog shows incorrect parents |
7.4.7 |
Potential crash when selecting a non parent destination entity for port push-up |
| 1310 |
Changing object colors has delayed effect. |
7.4.6 |
Changes to object colors in user settings only take effect after restarting Ease. |
| 1308 |
Net without connections |
7.4.6 |
Copy & paste of CBN tags can result in empty nets causing warning messages |
| 1304 |
Editing multiple connect by tags |
7.4.6 |
Editing multiple connect by tags propagates the name of the first tag to all others. |
| 1302 |
use clause for Xilinx unisim component cause syntax errors with ISE synthese |
7.4.5 |
Use clauses like:
use unisim.bufgp.all;
cause an syntax error when the component is instantiated in the architecture. |
| 1301 |
No way to generate an entity from the command line without generating the architectures |
7.4.5 |
When trying to generate HDL for a single entity using the hdlgen.tcl command
line script using the "-output unit" and -single options the architectures are
also generated. There is no way to generate only the entity without generation
the architectures or (if there is more than one architecture) to generate the
entity with only one of the architectures. |
| 1296 |
Verilog localparam in instance map |
7.4.4 |
Verilog localparam may not appear in the instance map of the instantiating module. |
| 1295 |
Only one option allowed in the file registration dialog. |
7.4.4 |
Options specified in the arguments field are used as a single options. |
| 1294 |
Project stays modified |
7.4.4 |
Option show full entity declaration in architecture HDL file causes repeated modifications |
| 1292 |
Print all diagrams missing diagrams |
7.4.4 |
Print all diagrams in a library does not print hierarchical FSM diagrams |
| |
Added Lattice Diamond to the toolflow. |
7.4.3 |
As title |
| |
Changed Xilinx project file extension. |
7.4.3 |
The Xilinx project file extension changed from .ise to .xise |
| 1290 |
The user specific project file was not always saved |
7.4.3 |
The user specific project settings (project.xml file) were not always saved
when a project was closed. This file contains data like the location of the
toplevel marker and the last HTML output directory.
|
| 1287 |
Component library objects are added to the toolflow |
7.4.2 |
All files for packages and entities in a component library are included in the toolflow. |
| 1286 |
Erroneous duplicate name error |
7.4.2 |
If that same signal name is used in different generate blocks belonging to the
same architecture Ease will issue an error about a duplicate signal name. |
| 1285 |
HDL output written to file without extension when using one file per library option |
7.4.2 |
If no file output file is specified for a library and the use one file per
library output generation is set the generated file will not have an extension.
This may cause problems when using external tools that determine the language
based on the file extension (e.g. .vhd or .v). |
| 1277 |
When re-importing packages the package uses for these packages will be lost |
7.4.1 |
When re-importing the user package it was first deleted causing deletion of all
use clauses referring to the user package. The use clauses are no longer
deleted when deleting the user package during re-import. |
| 1272 |
Allow more flexibility in the clock enable of an FSM |
7.4.1 |
It would be nice if expression where allowed as clock enable expressions instead of only signals. |
| 1271 |
Not possible to set attribute on component |
7.4.1 |
It is not currently possible to set an attribute for a component. Code placed
in the 'Declarations after signals' section will be inserted before the
component declarations so referring to the components here will result in
errors. We need a new 'Declarations after components' section to deal with
this. |
| 1265 |
Can only import one library from another project at the same time |
7.4.1 |
When importing libraries from another project we need to import them one by
one. Sometimes we need to import 10 libraries from the same project and it
would be nice if we could do this in a single action. |
| 1264 |
Support for import of Verilog generate statements |
7.4.1 |
Currently it is not possible to import all Verilog generate statements. |
| 1234 |
Improve placement components 'testbench skeleton creation' |
7.4.1 |
The monitor and dut components are placed against each other resulting in wires
across the components |
| 1221 |
Configuration don't support architectures in external VHDL files |
7.4.1 |
As title |
| 1194 |
Add support for external architectures |
7.4.1 |
Please add support for external architectures. When using an architecture HDL
file it is not possible to modify the file directly from the
simulator/compiler. When you navigate to the 'source' code from external tools
you will end up in the generated Ease code and not the real source. It does not
make sense to have duplicate code here so it would be nice to have an
'external' architecture. |
| 1191 |
Place LIBRARY statement within pragmas |
7.4.1 |
When a systhesis pragma is used for a package use the library declaration is
written without pragma. This results in warnings when using Synopsis Design Compiler |
| 1125 |
Add variables to interface list in FSM action properties dialog |
7.4.1 |
Beside port names the interface list in the FSM action properties dialog should
also contain information about local signals and variables declared in included
text sections. |
| 1028 |
Generate use clauses in skeleton for architecture HDL file |
7.4.1 |
Please generate the use clauses inside the skeleton header for architecture HDL files. |
| 1027 |
Generate entity declaration in skeleton for architecture HDL file |
7.4.1 |
Please generate the entity declaration in the skeleton for the architecture HDL
file (not in comment). We are using an external editor (SlickEdit) that will do
syntax checking and highlighting based on the definitions in the entity
(ports/generics). |
| 980 |
FSM sensitivity lists |
7.4.1 |
It does not appear to be possible to add internal user-defined signals to the
sensitivity lists of FSM's. Is there any way that this coud be incorporated
through a series of dialogues ? This would have to take into account the HDL
output style so may be more complex than initially thought. This is required to
elminate warnings about incomplete sensitivity lists during synthesis.
|
| 978 |
Moving up the design hierarchy |
7.4.1 |
When moving up the design hierarchy by double clicking the white space in a
block diagram, it would be useful to highlight the block that you've just come
up from, perhaps by leaving it selected. |
| 877 |
Improve error message for duplicate names |
7.4.1 |
When a net has the same name as an entity, the verification reports that the
netname is already declared in this region. The report should also contain where (entity) the name is also declared. |
| 33 |
FSM imcluded texts will never be on the sensitivity list of the state machine |
7.4.1 |
You can define FSM included texts (signal declarations), but these signals can
not be put in the sensitivity list of the state machine. |
