| 1235 |
Infinit loop in Rule Matcher |
1.3.4 |
The rule matcher will go into a an infinite loop when a rule is created for a PCB signal that contains the '$' character in its name. |
| 1232 |
Reference designator searched case sensitive. |
1.3.4 |
Reference designator is searched case sensitive in the Cadence Allegro pstxprt.dat file. |
| 1230 |
Constraint assignments are case sensitive for HDL signals |
1.3.3 |
Imported HDL signals refer case sensitive to the constraint data. |
| 1229 |
Record support in VHDL Entity portlist. |
1.3.3 |
As title |
| 1228 |
LVDS negative written incorrectly to constraint file. |
1.3.2 |
The LVDS negative constraint indication (n) is written as [n] in the Altera constraint file. |
1227 |
Altera constraint reader doesn't remove quotes. |
1.3.2 |
Double quotes placed around a constraint name are not stripped. |
| 1222 |
Device change not properly propagated. |
1.3.1 |
The Signal View is not properly updated when you selected a new device in the project properties. |
| 1195 |
Cadence packager netlist parser fails. |
1.3.1 |
The Cadence packager netlist parser fails on nets with the name '+' or '-' |
| 1182 |
Cadence board extraction is case sensitive for the refdes. |
1.3.1 |
The results of the extract on the Cadence board file is done case sensitive for the reference designator. |
