| |
Device release |
2.1.4 |
Device update for Xilinx (Artix-7/Kintex-7/Virtex-7) |
| 1356 |
No voltage check is done on promoted ground or power pins |
2.1.4 |
No voltage check is done on user IO pins that are promoted to ground or power
pins to allow device migration. |
| |
Device release |
2.1.3 |
Device update for Xilinx (Artix-7/Kintex-7/Virtex-7) and Altera (Arria V/Stratix V/ Cyclone V) |
| 1289 |
Mentor Board Station netlist parser improvement |
2.1.2 |
Mentor Board Station netlist allows '=' character in identifiers |
| 1288 |
Dangling net property not correctly cleared on re-import |
2.1.2 |
As title |
| 1275 |
Support DxDesigner 'Quick Connection View' |
2.1.1 |
DXDesigner has a Quick Connection View' format. When generated using the
options 'Flat mode' and 'Compress Flat Nets' it contains the information necessary in IO Checker. |
| 1251 |
New rule should enabled by default |
2.1.1 |
|
| 1239 |
Add user accepted flag on power errors. |
2.1.1 |
Some signals like VCCBAT are sometimes connected to GND while the pin list specifies VCC, it would be nice to suppress the power error. |
