Verilog Reference Guide

This reference guide contains information about most items that are available in the Verilog language. All subjects contain one or more examples and link(s) to other subjects that are related to the current subject.

This reference guide is not intended to replace the IEEE Standard Verilog Language Reference Manual (LRM), IEEE STD 11364-1995. For most subjects, the LRM section(s) is mentioned where you can find the formal description of the subject.

The Verilog syntax description in this reference manual uses the following grammar:

• Syntax enclosed in square brackets [ ] is optional.
• Curly brackets { } enclose comment. This comment is not part of the Verilog syntax, but gives more information about the syntax. The Verilog comment syntax, two adjacent slashes //, has the same meaning.
• Bold words are reserved words in the Verilog language.
• Underlined syntax belongs to the Verilog-2001 language, but not to the Verilog-1995.