A configuration specifies the version and location of a module.

Syntax:

config configuration_name;
  design [ library. ]toplevel_module;
  [ default liblist library library ...; ]
  [ instance_or_cell name location; ]
endconfig

instance_or_cell = instance | cell
location = liblist library | use what_to_use
what_to_use = [ library. ]instance [ : configuration_name ] | configuration_name 

Description:

A configuration specifies the exact version and source location of each Verilog module. The configuration is specified outside the module declaration, so the Verilog module does not need to be modified to reconfigure a design. The configuration name exists in the same namespace as module and primitive names.

Virtual libraries are used in the configuration. The virtual libraries are associated with physical locations with a separate library map file.

Example:

config Cfg;
  design rtlLib.top;                         // toplevel module
  default liblist rtlLib gateLib;            // virtual library search order
  instance top.sub.u1 liblist gateLib;
  cell top.sub.u2 use gateLib.mux;
  instance top.sub.u3 use Cfg2;
endconfig

// separate library map file
library rtlLib ./*.v;
library gateLib ../../synth/*.v;

See also:

Instantiation, Module