A function groups statements together and returns the value that is assigned to the function name.

Syntax:

function [ automatic ] [ size_or_type ] function_name;
  input_declaration
  [ local_declaration ] 
  statement
endfunction 

input_declaration = input [ size ] input_name, ...;

Description:

A function groups statements together to define new mathematical or logical functions. It is declared inside a module, and is usually called only from that module. Declarations within a function are statically allocated, and are shared by all function calls.

A function must have at least one input argument. It may not have any inouts or outputs.

The size_or_type is the return bit range as [msb:lsb], or the types integer or real.

The statements must be enclosed in a begin-end or fork-join block if the function contains more than one statement.

A function can be declared as automatic (Verilog-2001), which allows the function to be called recursively. Declarations within the function will be allocated dynamically for each recursive call. Declarations within an automatic function cannot be accessed by hierarchical references.

Example:

function [7:0] ReverseBits;
  input [7:0] Byte;
  integer I;
  begin
    for (I = 0; I < 8; I = I + 1)
      ReverseBits[7 - I] = Byte[I];
  end
endfunction 

Notes:

• Functions may not contain timing controls.
• Functions may not enable tasks.
• Functions may not be disabled.

See also:

Function call, Task