Reserved Words |
LRM §2.7.2. |
The reserved words are reserved for significance in the Verilog language.
Description:
The reserved words cannot be used as explicitly declared identifiers. The table below shows all reserved words.
always |
edge |
highz0 |
nand |
rcmos |
table |
wait |
and |
else |
highz1 |
negedge |
real |
task |
wand |
assign |
end |
|
nmos |
realtime |
time |
weak0 |
automatic |
endcase |
if |
nor |
reg |
tran |
weak1 |
|
endconfig |
ifnone |
noshowcancelled |
release |
tranif0 |
while |
begin |
endfunction |
initial |
not |
repeat |
tranif1 |
wire |
buf |
endgenerate |
inout |
notif0 |
rnmos |
tri |
wor |
bufif0 |
endmodule |
input |
notif1 |
rpmos |
tri0 |
|
bufif1 |
endprimitive |
instance |
|
rtran |
tri1 |
xnor |
|
endspecify |
integer |
or |
rtranif0 |
triand |
xor |
case |
endtable |
|
output |
rtranif1 |
trior |
|
casex |
endtask |
join |
|
|
trireg |
|
casez |
event |
|
parameter |
scalared |
|
|
cell |
large |
pmos |
showcancelled |
use |
|
|
cmos |
for |
liblist |
posedge |
signed |
||
config |
force |
localparam |
primitive |
small |
vectored |
|
forever |
|
pull0 |
specify |
|||
deassign |
fork |
macromodule |
pull1 |
specparam |
|
|
default |
function |
medium |
pulldown |
strong0 |
|
|
defparam |
|
module |
pullup |
strong1 |
|
|
design |
generate |
|
pulsestyle_ondetect |
supply0 |
|
|
disable |
genvar |
|
pulsestyle_onevent |
supply1 |
|
|
Notes: