Sensitivity list

LRM §9.7.

The sensitivity list controls when the statements in an always block are evaluated.


@( [ edge ] signal [ or [ edge ] signal ] ... )
@( [ edge ] signal [ , [ edge ] signal ] ... )

edge = posedge | negedge


The sensitivity list controls when all statements in the always block will start to be evaluated.

In Verilog-1995 the signals are separated by the keyword or. In Verilog-2001 the signals may be separated by a comma. This new comma-separated sensitivity list does not add new functionality. It does make the Verilog syntax more intuitive, and more consistent with other signal lists in Verilog.

The sensitivity list must include all input signals used by an always block to properly model combinational logic. It is easy to inadvertently omit an input signal from the sensitivity list, which can lead to simulation and synthesis mismatches.

Verilog-2001 adds a new wild card token, @*, which represents a combinational logic sensitivity list. The @* token adds to the sensitivity list all nets and variables that are read by the statements in the always block.


always @(posedge Clk or negedge Reset)
always @(negedge Reset, Enable)
always @*                          // same as @(A or B or C or D)
  Tmp1 = A & B;
  Tmp2 = C & D;

See also:

Always, Procedural timing control