Basic Modelling
Every VHDL design description consists of at least one entity/architecture pair. In a large design, you will typically write many entity/architecture pairs and connect them together to form a complete circuit.
An entity declaration describes the circuit as it appears from the outside world, its input and output interfaces (ports and generics). In a schematic design, you might think of an entity declaration as being analogous to a block symbol on a schematic.
An entity declaration provides the complete interface for a circuit. You have all information you need to connect that circuit into other, higher-level circuits.
The architecture declaration is the second part of a minimal VHDL design. The architecture describes the actual function, or contents, of the entity to which the architecture is bound. In a schematic design you can think that an architecture is analogous to a lower-level schematic referenced by the higher-level functional block symbol.
One way of describing the function of an entity is to describe how it is composed of sub-components. Each of the sub-components is an instance of some entity, and the interface of the instances are connected together using signals. A signal represents an electrical connection, a wire or a bus. A port map is used to connect signals to the ports of an instantiation, where a port represents a pin. This kind of description is called a structural.
Another way of describing the function of an entity is in terms of programming language notations. This is called a behavioural or functional description. The behaviour is described using processes. Each process executes concurrently with respect to all other processes. Statements inside a process execute in sequential order.
A configuration specifies which architecture is bound to which entity, and it allows to change the component connection (via a port map and generic map).
Configurations are always optional, no matter how complex the design description. When no configuration has been declared, the VHDL standard specifies a set of rules that provides a default configuration. For example, when an entity has more than one associated architecture, the last architecture compiled will be bound to the entity.