Operator overloading is a declaration of a function whose designator is an operator symbol.
The operator is called overloaded if there is more than one function specifying it for different data and result types. VHDL allows defining operators of the same names as predefined operators, but for different operand types. Both can exist together in one specification, offering greater versatility to the user.
All synthesis tools provide a package which contains overloaded operators and functions. Typically they include the operators + - = /= < <= > >= which are overloaded on type std_logic_vector.
type NewType is ('0', '1', 'Z', 'X'); function "nand" (Left, Right: NewType) return NewType; function "or" (Left, Right: NewType) return NewType; signal A, B, C: NewType; C <= (A nand B) or 'X';