The reserved words are reserved for significance in the  VHDL language.

Description:

The reserved words cannot be used as explicitly declared identifiers. The table below shows all reserved words.

Notes:

• VHDL is case insensitive, therefore there is no difference using either uppercase or lowercase for reserved words.
• If an identifier is placed between leading and trailing backslashes, it becomes an extended identifier and is no longer a reserved word (e.g. \port\ is not a reserved word).
• Predefined names (e.g. Event, Left, Length, Integer, Bit, true) are not reserved words. But using them as identifiers can cause confusion!