HDL WORKS PRESENTS IO CHECKER 3.3
November 2016, HDL Works announces the release and immediate availability of IO Checker 3.3,
the FPGA and PCB IO verification tool.
About IO CheckerIO Checker will verify that signal names used in the FPGA are connected to the appropriate signals on the PCB. Additionally it verifies the voltage values connected to the FPGA power and reference pins. IO Checker uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins.
The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pin device in half an hour.
What is new in IO Checker 3.3
Wiring interface for schematic capture
The wiring interface allows you to add/remove wires and IO ports to a Altium Designer or Cadence Allegro schematic based on the FPGA constraints or pin data. For power and ground pins you can add a wire or place a note about the required voltage near the pin. The interface can be run multiple times to accommodate changes in the pin-out of the device. It is also possible to use the CSV import to add wires and port to the schematic. The available options depend on the selected schematic capture system. pull-down circuits.
Improved FPGA device settings page
The FPGA device page has an extra 'Category' field and a 'Show legacy families' check-box. The 'Category' field helps to decrease the amount of families listed in the 'Family' drop-down box. When the 'Show legacy families' check-box is selected the older FPGA families for a vendor are shown as well.
Xilinx Vivado reader
The Vivado pin placement report file doesn’t report voltage information for power pins like VCCINT, VCCAUX and MGTA_VTT. This information is however present in the power report file and IO Checker will process this file (when present) to propagate voltage information to power pins. On average it delivers an extra 10% signals which can automatically be verified.
Cadence Allegro ‘chipfile‘ pin group editor
The pin group editor allows you to edit the chips.prt file of an FPGA and define the PIN_GROUP values for it. Pins which have the same group can be swapped in the Allegro board environment. The groups can be defined automatically (based on IO bank) or manually.
Support has been added or updated for Altera Arria10 and MAX10 and Xilinx Kintex/Virtex/Zynq UltraScale and UltraScale+ devices.
Availability and Pricing
IO Checker 3.3 is available now. Prices begin at € 750 or US$1,125. IO Checker can be downloaded and evaluated from the HDL Works website.
About HDL Works
HDL Works develops and markets high-performance, intuitive tools for complex HDL design across a wide spectrum of applications. HDL Works currently holds ConnTrace, EASE, HDL Companion and IO Checker in its product portfolio. Headquartered in Ede, The Netherlands, HDL Works is privately held.HDL Works BV
6716 BX Ede
ConnTrace, EASE, HDL Companion, IO Checker and Scriptum are trademarks of HDL Works.