HDL WORKS PRESENTS IO CHECKER 3.4
January 2018, HDL Works announces the release and immediate availability of IO Checker 3.4,
the FPGA and PCB IO verification tool.
About IO CheckerIO Checker will verify that signal names used in the FPGA are connected to the appropriate signals on the PCB. Additionally it verifies the voltage values connected to the FPGA power and reference pins. IO Checker uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins.
The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pin device in half an hour.
What is new in IO Checker 3.4
Undo / redo
The transformation from a pure verification tool to a design tool (to create constraints or update schematic pages) has lead to the need of undo/redo functionality. Any change in a project can now be un-done using the undo button or the short-cut key ctrl-z. An undo action itself can be undone with a redo (shortcut key: ctrl-r).
Functional pin name
In the previous versions of IO Checker the full functional pin name was only visible in tool-tips. When a designer is busy with determining a pin-out for an FPGA it is useful to see the full functional pin name. The signal view is therefor extended with 2 new columns: ‘FPGA functional name’ and ‘Pin group’. These columns are hidden by the view column filter for a new project (to limit the number of columns) but can be enabled at any time.
Pin view name filterThe pin view text filter allows you to filter (show) the rows in which the specified text (or part of) appears. This makes it easy to just visualize all VREF pins, by specifying VREF. Showing all memory capable DQS pins can be done using the text string ‘dqs’. The filter is applied for all visible columns in the view. When you close the filter widget, the filter is cleared. The text filter is independent of the row filter.
PCB voltage recognition and visualization
When company or user power configurations are present they will be processed before the installation version.
This allows you to overrule the defaults in the installation.
It was not always obvious which voltage IO Checker had extracted from the PCB netlist. In IO Checker 3.4 the recognized voltage is displayed after the signal name. Like: '+3V3D (= 3.3), or (↑ 3.3V) for a pull-up voltage of 3.3V.
CSV export / import
The Pin list view in IO Checker can now be exported to a comma separated values file. A dialog allows you to select which column data and which rows to export. A new import HDL data from CSV file allows you to import data as if it was a VHDL entity or Verilog module. This dialog works like the already present FPGA CSV constraint import, but the imported signals are shown in the HDL view. Ranges can be specified in the signal name using sig<0:15> or sig[0:15] or using a consecutive range of indices: sig, sig, sig
A new option to import HDL data from a CSV file allows you to import data as if it was a VHDL entity or Verilog module.
This dialog works like the already present FPGA CSV constraint import, but the imported signals are shown in the HDL view.
Ranges can be specified in the signal name using sig<0:15> or sig[0:15] or using a consecutive range of indices: sig, sig, sig etc.
A new quick view button (present when a file must be specified) allows you to pre-view the file contents.
Altium Designer extensionHDL Works has modified (and improved) the Altium Designer extension to be able to use IO Checker projects directly in Altium Designer. When a schematic page is open in AD you can start the IO Checker dialog. The extension allows you to:
Start the verification of FPGA schematics versus a pin-out file, constraints or user specification.
- Add wires (and IO ports) to the symbols of an FPGA instantiated on different schematic pages based on the FPGA pin file, design constraints, or a CSV file. This can be done for an individual part of a component, a sheet, or for all components of the FPGA (on multiple schematic pages).
Cadence Allegro CSV wiringThe Cadence Allegro wiring functionality for FPGA’s has been extended to also wire non-FPGA components based on a comma separated value (CSV) file. It can be used to wire any kind of component (from connector to processor).
The dialog is started through a TCL command and works independent of the project open in IO Checker. The format of the CSV file is fully configurable in the dialog.
Device SupportThe following device families (or additional devices) have been added:
- Altera: Cyclone 10, Arria 10, Stratix 10
- Lattice: ECP 5, XO 2
- Xilinx: Spartan 7, Kintex Ultrascale+, Virtex Ultrascale+, Zynq Ultrascale+
Availability and Pricing
IO Checker 3.4 is available now. Prices begin at € 750 or US$1,125. IO Checker can be downloaded and evaluated from the HDL Works website.
About HDL Works
HDL Works develops and markets high-performance, intuitive tools for complex HDL design across a wide spectrum of applications. HDL Works currently holds ConnTrace, EASE, HDL Companion and IO Checker in its product portfolio. Headquartered in Ede, The Netherlands, HDL Works is privately held.HDL Works BV
6716 BX Ede
ConnTrace, EASE, HDL Companion, IO Checker and Scriptum are trademarks of HDL Works.