HDL WORKS PRESENTS IO CHECKER 4.0
March 2019, HDL Works announces the release and immediate availability of IO Checker 4.0,
the FPGA and PCB IO verification tool.
About IO CheckerIO Checker will verify that signal names used in the FPGA are connected to the appropriate signals on the PCB. Additionally it verifies the voltage values connected to the FPGA power and reference pins. IO Checker uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins.
The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pin device in half an hour.
What is new in IO Checker 4.0
The HDL view has been transformed into the Signal view. The user can modify all properties of the signals (like name, range, direction, location constraint) and add or delete signals. The data in the Signal view can be:
- imported from a VHDL/Verilog file
- populated from constraint files
- imported from a CSV file
- created from PCB data
- user defined
- create constraints
- create a VHDL entity or Verilog module
- used in the wiring interface
- exported to a CSV file
CSV importThe HDL CSV import and FPGA CSV data import are replaced by a single CSV import that will import data into the Signal view. The import will merge the data found in the file with data already present in the Signal view. Signals already present in the view but not in the import are not removed. The dialog has a ‘Determine import settings‘ button to automatically determine the comment character, column separator and FPGA pin name.
VerificationThe verification is now task driven instead of source driving. The new approach makes it easier to perform a specific verification task. The verification mode specified in the wizard will be used as the default mode during verification.
The individual verification tasks can also be started from the Verify menu.
The matching rules dialog has an extra checkbox, that allows you to use the derived PCB signal name in the matching rules. This is very useful when signals are tied to ground using a resistor, and the direct signal name is a system generated name. In the example below pin AT14 is functionally connected ground (over a resistor). Using the checkbox ‘derived’ in the Rules dialog this can automatically be verified.
FPGA pin file processingSeveral improvements were made to the pin file readers:
Extract vref pin data from the pin layout file.
Support for default IO standard (STRATIX_DEVICE_IO_STANDARD) in the constraint file.
Unused signals in Xilinx are now reported in the pin view as <UNUSED> instead of using the pin functional name (like <IO_L11N_6>). This allows the rule engine to create rules for them.
Improved recognition of drive strength and slew rate.
Device SupportThe following device families (or additional devices) have been added:
- Altera: Cyclone 10, Arria 10, Stratix 10
- Microsemi: PolarFire
- Xilinx: Virtex UltraScale+ HBM, Defense-Grade Zynq UltraScale+ RFSoC / MPSoC
Availability and Pricing
IO Checker 4.0 is available now. Prices begin at € 750 or US$1,125. IO Checker can be downloaded and evaluated from the HDL Works website.
About HDL Works
HDL Works develops and markets high-performance, intuitive tools for complex HDL design across a wide spectrum of applications. HDL Works currently holds ConnTrace, EASE, HDL Companion and IO Checker in its product portfolio. Headquartered in Ede, The Netherlands, HDL Works is privately held.HDL Works BV
6716 BX Ede
ConnTrace, EASE, HDL Companion, IO Checker and Scriptum are trademarks of HDL Works.