What's new in EASE™ 9.1

VHDL attribute specifications

In Ease 9.1 it is possible to declare attribute values on entities, architectures, instances and nets. The attributes themselves must be declared in packages, for which a use clause must have been added to the entity or architecture. A drop down box will show all visible attributes. For each used attribute a tool tip can show the type and package where the attribute is defined. The attributes are placed in the generated VHDL code just before the start of the architecture, block or generate statement.

VHDL Attributes
VHDL Attributes

Clauses at architecture level

Library clauses, use clauses and context references can now be added to an architecture in the same way as for an entity.

HDL Import improvements

VHDL import now tries to import comment for the following objects:
  • entity generics
  • entity ports
  • signal declarations
  • component instantiation statements
  • generate statements

Other improvements


Supported platforms

Windows (64-bit only): Windows 7 / 8.1 / 10
Linux (64-bit only): Should work with any recent distribution.
Tested with RHEL 6 and RHEL 7.

More about EASE

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