What's new in IO Checker 3.3
Wiring interface for schematic capture
The wiring interface allows you to add/remove wires and IO ports to a Altium Designer or Cadence Allegro schematic based on the FPGA constraints or pin data. For power and ground pins you can add a wire or place a note about the required voltage near the pin. The interface can be run multiple times to accommodate changes in the pin-out of the device. It is also possible to use the CSV import to add wires and port to the schematic. The available options depend on the selected schematic capture system.
Automatically adding wires to components of a large FPGA saves valuable time and guarantees equal signal names in both design environments.
Improved FPGA device settings page
The FPGA device page has an extra 'Category' field and a 'Show legacy families' check-box.
The 'Category' field helps to decrease the amount of families listed in the 'Family' drop-down box.
When the 'Show legacy families' check-box is selected the older FPGA families for a vendor are shown as well.
The legacy families are:
- Altera: Cyclone I, II and III, MAX II, Stratix I, II, III and Arria GX
- Lattice: XP2, ECP2
- Xilinx: Spartan 3 (all), Virtex 4
Xilinx Vivado reader
The Vivado pin placement report file doesn’t report voltage information for power pins like VCCINT, VCCAUX and MGTA_VTT. This information is however present in the power report file and IO Checker will process this file (when present) to propagate voltage information to power pins. On average it delivers an extra 10% signals which can automatically be verified.
Cadence Allegro ‘chipfile‘ pin group editor
The pin group editor allows you to edit the chips.prt file of an FPGA and define the PIN_GROUP values for it. Pins which have the same group can be swapped in the Allegro board environment. The groups can be defined automatically (based on IO bank) or manually.
Device SupportThe following device families (or additional devices) have been added:
The complete list of supported FPGA families can be found on the FPGA page.
- Use VOLTAGE property (when present) in Allegro board file processing to determine voltage of power nets.
- Made vector recognition in the PcbToConstraints and PcbToHDL dialogs configurable.
- Improved ‘Constraint present’ indicator in the device view.
- The Windows version is now also 64 bit. (Windows Vista is no longer supported.)