What's new in IO Checker™ 3.4

Undo / redo

The transformation from a pure verification tool to a design tool (to create constraints or update schematic pages) has lead to the need of undo/redo functionality. Any change in a project can now be un-done using the undo button or the short-cut key ctrl-z. An undo action itself can be undone with a redo (shortcut key: ctrl-r).

Functional pin name

In the previous versions of IO Checker the full functional pin name was only visible in tool-tips. When a designer is busy with determining a pin-out for an FPGA it is useful to see the full functional pin name. The signal view is therefor extended with 2 new columns: ‘FPGA functional name’ and ‘Pin group’. These columns are hidden by the view column filter for a new project (to limit the number of columns) but can be enabled at any time.

Pin view name filter

The pin view text filter allows you to filter (show) the rows in which the specified text (or part of) appears. This makes it easy to just visualize all VREF pins, by specifying VREF. Showing all memory capable DQS pins can be done using the text string ‘dqs’. The filter is applied for all visible columns in the view. When you close the filter widget, the filter is cleared. The text filter is independent of the row filter.
IO Checker Pin view showing pin functional name in combination with an filter
IO Checker Pin view showing pin functional name in combination with an filter

PCB voltage recognition and visualization

When company or user power configurations are present they will be processed before the installation version. This allows you to overrule the defaults in the installation.
It was not always obvious which voltage IO Checker had extracted from the PCB netlist. In IO Checker 3.4 the recognized voltage is displayed after the signal name. Like: '+3V3D (= 3.3), or (↑ 3.3V) for a pull-up voltage of 3.3V.

IO Checker Pin view showing netlist information
IO Checker Pin view showing netlist information

CSV export / import

The Pin list view in IO Checker can now be exported to a comma separated values file. A dialog allows you to select which column data and which rows to export. A new import HDL data from CSV file allows you to import data as if it was a VHDL entity or Verilog module. This dialog works like the already present FPGA CSV constraint import, but the imported signals are shown in the HDL view. Ranges can be specified in the signal name using sig<0:15> or sig[0:15] or using a consecutive range of indices: sig[0], sig[1], sig[2]

A new option to import HDL data from a CSV file allows you to import data as if it was a VHDL entity or Verilog module. This dialog works like the already present FPGA CSV constraint import, but the imported signals are shown in the HDL view. Ranges can be specified in the signal name using sig<0:15> or sig[0:15] or using a consecutive range of indices: sig[0], sig[1], sig[2] etc.
A new quick view button (present when a file must be specified) allows you to pre-view the file contents.

CSV Export dialog
CSV Export dialog

Altium Designer extension

HDL Works has modified (and improved) the Altium Designer extension to be able to use IO Checker projects directly in Altium Designer. When a schematic page is open in AD you can start the IO Checker dialog. The extension allows you to:
  1. Start the verification of FPGA schematics versus a pin-out file, constraints or user specification.
  2. Add wires (and IO ports) to the symbols of an FPGA instantiated on different schematic pages based on the FPGA pin file, design constraints, or a CSV file. This can be done for an individual part of a component, a sheet, or for all components of the FPGA (on multiple schematic pages).
The extension is available for Altium Designer versions 15/16/17 and 18.
Altium IO Checker dialog
Altium IO Checker dialog

Cadence Allegro CSV wiring

The Cadence Allegro wiring functionality for FPGA’s has been extended to also wire non-FPGA components based on a comma separated value (CSV) file. It can be used to wire any kind of component (from connector to processor).

The dialog is started through a TCL command and works independent of the project open in IO Checker. The format of the CSV file is fully configurable in the dialog.
Allegro CSV wiring dialog

Device Support

The following device families (or additional devices) have been added:

The complete list of supported FPGA families can be found on the FPGA page.

Enhancements

Download IO Checker 3.4 now:


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