What's new in IO Checker 3.4
Undo / redo
The transformation from a pure verification tool to a design tool (to create constraints or update schematic pages) has lead to the need of undo/redo functionality. Any change in a project can now be un-done using the undo button or the short-cut key ctrl-z. An undo action itself can be undone with a redo (shortcut key: ctrl-r).
Functional pin name
In the previous versions of IO Checker the full functional pin name was only visible in tool-tips. When a designer is busy with determining a pin-out for an FPGA it is useful to see the full functional pin name. The signal view is therefor extended with 2 new columns: ‘FPGA functional name’ and ‘Pin group’. These columns are hidden by the view column filter for a new project (to limit the number of columns) but can be enabled at any time.
Pin view name filterThe pin view text filter allows you to filter (show) the rows in which the specified text (or part of) appears. This makes it easy to just visualize all VREF pins, by specifying VREF. Showing all memory capable DQS pins can be done using the text string ‘dqs’. The filter is applied for all visible columns in the view. When you close the filter widget, the filter is cleared. The text filter is independent of the row filter.
PCB voltage recognition and visualization
When company or user power configurations are present they will be processed before the installation version.
This allows you to overrule the defaults in the installation.
It was not always obvious which voltage IO Checker had extracted from the PCB netlist. In IO Checker 3.4 the recognized voltage is displayed after the signal name. Like: '+3V3D (= 3.3), or (↑ 3.3V) for a pull-up voltage of 3.3V.
CSV export / import
The Pin list view in IO Checker can now be exported to a comma separated values file. A dialog allows you to select which column data and which rows to export. A new import HDL data from CSV file allows you to import data as if it was a VHDL entity or Verilog module. This dialog works like the already present FPGA CSV constraint import, but the imported signals are shown in the HDL view. Ranges can be specified in the signal name using sig<0:15> or sig[0:15] or using a consecutive range of indices: sig, sig, sig
A new option to import HDL data from a CSV file allows you to import data as if it was a VHDL entity or Verilog module.
This dialog works like the already present FPGA CSV constraint import, but the imported signals are shown in the HDL view.
Ranges can be specified in the signal name using sig<0:15> or sig[0:15] or using a consecutive range of indices: sig, sig, sig etc.
Altium Designer extensionHDL Works has modified (and improved) the Altium Designer extension to be able to use IO Checker projects directly in Altium Designer. When a schematic page is open in AD you can start the IO Checker dialog. The extension allows you to:
Cadence Allegro CSV wiringThe Cadence Allegro wiring functionality for FPGA’s has been extended to also wire non-FPGA components based on a comma separated value (CSV) file. It can be used to wire any kind of component (from connector to processor).
The dialog is started through a TCL command and works independent of the project open in IO Checker. The format of the CSV file is fully configurable in the dialog.
Device SupportThe following device families (or additional devices) have been added:
- Cyclone 10 LP
- Cyclone 10 GX
- Arria 10
- Stratix 10
- ECP 5
- XO 2
- Spartan 7
- Kintex Ultrascale+
- Virtex Ultrascale+
- Zynq Ultrascale+
The complete list of supported FPGA families can be found on the FPGA page.
- Id 1240: Legend for the symbols in the device view.
- Id 1626: Use of derived PCB signal name in the matching rules.
- Id 1824: Tooltips in the rules dialog to see which signals match in the rule.
- Id 1848: New Help about dialog with links to the website.
- Wire a non FPGA symbol in Cadence Allegro based on CSV data
- Tooltip on the sort button in the signal view shows the order set
- HDL generator dialog retains options and values set with the active session.
- Customer power rules are loaded before the installation file.
- Tooltip on the filter buttons in the pin and hdl view show the filters set.
- A voltage divider based on 2 resistors is now recognized.
- A new pin group named Rref is added, for FPGA pins that need to connected to ground using a resistor.
- Extract low level wire names from Cadence Allegro schematics.
- The HTML report now shows the icon images in the pin view.
- Simplified drag&drop behavior for signal assignment for LVDS pairs.