What's new in IO Checker 4.0
The HDL view has been transformed into the Signal view. The user can modify all properties of the signals (like name, range, direction, location constraint) and add or delete signals. The data in the Signal view can be:
- imported from a VHDL/Verilog file
- populated from constraint files
- imported from a CSV file
- created from PCB data
- user defined
- create constraints
- create a VHDL entity or Verilog module
- used in the wiring interface
- exported to a CSV file
CSV importThe HDL CSV import and FPGA CSV data import are replaced by a single CSV import that will import data into the Signal view. The import will merge the data found in the file with data already present in the Signal view. Signals already present in the view but not in the import are not removed. The dialog has a ‘Determine import settings‘ button to automatically determine the comment character, column separator and FPGA pin name.
VerificationThe verification is now task driven instead of source driving. The new approach makes it easier to perform a specific verification task. The verification mode specified in the wizard will be used as the default mode during verification.
The individual verification tasks can also be started from the Verify menu.
The matching rules dialog has an extra checkbox, that allows you to use the derived PCB signal name in the matching rules. This is very useful when signals are tied to ground using a resistor, and the direct signal name is a system generated name. In the example below pin AT14 is functionally connected ground (over a resistor). Using the checkbox ‘derived’ in the Rules dialog this can automatically be verified.
FPGA pin file processingSeveral improvements were made to the pin file readers:
Extract vref pin data from the pin layout file.
Support for default IO standard (STRATIX_DEVICE_IO_STANDARD) in the constraint file.
Unused signals in Xilinx are now reported in the pin view as <UNUSED> instead of using the pin functional name (like <IO_L11N_6>). This allows the rule engine to create rules for them.
Improved recognition of drive strength and slew rate.
Device SupportThe following device families (or additional devices) have been added:
- Intel (Altera)
- Cyclone 10 LP
- Cyclone 10 GX
- Arria 10
- Stratix 10
- Id 1956: Wire both LOCATION and $LOCATION in Cadence Allegro.
- Id 1977: Try to check if regular expressions used in rules dialog are valid.
- Support for Xilinx Vivado Floorplan files (.csv). (Please note that they do not contain power information, so you might as well use a constraint file)
- Signal view now supports copy to clipboard.
- File quick view items in dialogs now use a delay before showing file contents.
- Update dialog now has option to select all files for update in a single action.
- Improved power detection on PCB nets (support for negative voltages).
- New configuration file (array_rules.xml) to allow recognition of custom array styles.
- Verilog module generation is now done in the ANSI standard.
The complete list of supported FPGA families can be found on the FPGA page.