Fixed Problems in HDL Companion 2.11
October 24, 2018

SPRTitleReleasedDescription
2004 VHDL linter Misc2 (latch detected) false positive 2.11.1 VHDL linter reports Misc2 for conditional signal assignment inside clocked process.
1980 Performing drag & drop inside the File View reverses order 2.11.1 When dragging multiple directories around in the HDL Companion file view the directories are reversed in order at the new position.
1970 VHDL parser crash after syntax error (generic type) 2.11.1 When a generic type is used the actual type will refer to the first instantiation. If the architecture containing the instantiation contains syntax errors the actual type will be deleted, but the instantiated entity will still refer to the delete type information causing a crash.
1969 Incorrect VHDL CP7 lint message 2.11.1 When a user has used ieee.numeric_std_unsigned, the comparison operator for std_logic_vector is overloaded to allow numeric matches, even when the vector lengths do not match. In this case no CP7 lint message should be issued.
1968 VHDL linter CP7 false positive 2.11.1 Declaration:
    variable a: my_type(8 downto 0)(7 downto 0);
Reference:
    tmp := a(8);
Will result in a CP7 message 'index too high'. Index is checked against the last range of a instead of the first one.
1953 Incorrect VHDL-1724 parser error 2.11.1 Target of simple force assignment cannot be a member of a resolved composite signal
1943 VHDL linter CP14 false positive 2.11.1 VHDL linter does not use signals used in wait statements.
1935 Package declarations inside other units (packages, entities, architectures) are not supported 2.11.1 In VHDL 2008 package declarations (and package instantiations) are allowed inside other units.
1921 VHDL parser crash on syntax error 2.11.1 VHDL parser crashes on:
  myLabel: for k in mySignal'range to generate
1849 Add more info to 'Help about' dialog 2.11.1 From the 'Help about' dialog it should be possible to check if new versions/revisions are available.
1747 Verilog concatenated port declarations not visualized 2.11.1 Concatenated port declarations in the module definition, like:
   .control({ clk, rst})
are not shown in the detailed view.

Home dot Company dot Products dot Sales dot Support dot HDL Corner dot Site Map
Copyright © 2004 - 2019 HDL Works