Problems fixed in IO Checker 4.0
|2014||Verilog generated from PCB data contains wires declarations||4.0.1||Removed wires and generate ANSI style Verilog module|
|2012||MACHXO pins marked as dedicated control pins||4.0.1||MACHXO2 and MACHXO3 pins DONE, PROGRAMN and INNIT are set to be dedicated control (and not to be used in the constraints) while beeing dual use.|
|1977||Verify that the regular expression in rules dialog is valid||4.0.1||When you specify a regular expression like 'user_(\d+' there is no feedback that the expression is invalid. (Only that the match count will be 0)|
|1965||Wire both $LOCATION and LOCATION components||4.0.1||In some sheets in Cadence Allegro the FPGA components uses both LOCATION and $LOCATION reference designator. The wiring routine should support in the same sheet.|
|1942||Improve HDL/Constraint generation for Altium Designer LVDS signals||4.0.1||In Altium Designer it is required that all LVDS signal pairs end with _n and _p.
This is also the case for array signals.
So an LVDS array of signals in Altium Designer looks like:
sig<4>_p, sig<3>_p, ... (and n side, a<4>_n , a<3>_n).
|1923||Improve caption of verification window||4.0.1||IO Checker should adjust the caption when only doing a file status verification (vs a project verification).|
|1876||Add a check to verfiy all HDL signals have a location constraint||4.0.1||It is now only possible to see in the HDL Signal view if all signals have a pin location constraint. (Using the view filter).|
|1577||Improved generation of both HDL and constraint file from PCB data||4.0.1||HDL and constraint generation is now based on the Signal View. Here you can modify signal names, ranges and direction before generating HDL.|