Net Data Type |
LRM §3.2.1, §3.7, §6.1. |
Net data types connect structural components together.
net_type [ expansion ] [ size ] #( delay ) net_name, net_name, ...;
net_type [ expansion ] [ ( strength ) ] [ size ] #( delay ) net_name = expression; // declaration with
// continuous assignment
net_type [ size ] memory_name [ array_size [ array_size] ...; // Multi-dimensional array
expansion = scalared | vectored
Net data types are used to model connections in structural descriptions. They do not store values (except trireg). The net data types have the value of their drivers.
The Verilog LRM defines the following net types:
| wire or tri |
simple interconnecting wire |
| wor or trior |
wired outputs OR together |
| wand or triand |
wired outputs AND together |
| tri0 |
pulls down when tri-stated |
| tri1 |
pulls up when tri-stated |
| supply0 |
constant logic 0 (supply strength) |
| supply1 |
constant logic 1 (supply strength) |
| trireg |
stores last value when tri-stated (capacitance strength) |
A net data type must be used when:
If the keyword scalared is used, bit and part selects and strength specifications are permitted, and the PLI should consider the net 'expanded'. If the keyword vectored is used, bit and part selects and strength specifications may not be permitted, and the PLI may consider the net 'unexpanded'. These keywords are advisory.
wire [7:0] Data; trireg (large) C1; wire Q = A || B; // continuous assignment wire [7:0] Array [0:255][0:255][0:255]; // Verilog-2001 Multidimensional array