Register data types store values.

Syntax:

register_type [ size ] variable_name, variable_name, ...;
register_type [ size ] variable_name = initial_value;
register_type [ size ] memory_name [ array_size ]; 
register_type [ size ] memory_name [ array_size ] [ array_size ] ...;     // Multi-dimensional array

Description:

Register data types are used as variables in procedural blocks. They store logic values only (no logic strength).

The Verilog LRM defines the following register types:

A register data type must be used when the signal is on the left-hand side of a procedural assignment.

Verilog-2001 adds the ability to initialize variables at the time they are declared. The initial value assigned to the variable takes effect at simulation time zero, just as if the value had been assigned within an initial block.

Example:

reg [7:0] Data;
integer Int;
time Now;
reg [15:0] Memory [0:1023]; 
reg [7:0] A = 8'h3C;                      // Verilog-2001
reg [7:0] Array [0:255][0:255][0:255];    // Verilog-2001

Notes:

• Use reg for describing logic, integer for loop variables and calculations, real in system modules, and time and realtime for storing simulation times in testbenches.

See also:

Net data type, Procedural assignment