A set of values and a set of operations.

Syntax:

type type_name [ is data_type ]; 

Description:

All signals, variables, constants (i.e. objects) and expresssions have a type. The type defines the set of values that the object or expression can have. A type also determines the set of operations which can be performed on an object or expression.

There are four classes of types in VHDL:

• scalar types: represent a single numeric value, or in the case of enumerated types, an enumeration value.
• composite types: represent a collection of values.
• access types: provide access to objects of a given type.
• files: provide access to objects that contain a sequence of values of a given type (typically disk files).

Apart from predefined types (available through the packages Standard, Std_logic_1164 and Numeric_std), the user can define his own types. A user-defined type can be of any of the four classes mentioned above.

A value of one type cannot be assigned to an object of a different type. If a translation from one type to another is required, then type conversion must be applied.

Example:

type State is (TReset, TWait, THold, THalt);

Notes:

• VHDL is a strongly typed language which causes that two types defined in exactly the same way (i.e. lexically identical) but differing only by names will be considered different.
• The initial value of an object is the leftmost value of the type, i.e. the value on the left of the base enumeration.

See also:

Numeric_Std, Package, Standard Package, Std_logic_1164, Subtype, Type conversion