Type Conversion |
LRM §7.3.5. |
An expression that converts the value of a subexpression from one type to the designated type of the type conversion.
type_name ( expression )
VHDL is a strongly typed language. This causes that objects of even closely related types need a conversion, if they are supposed to be used together.
The result of the conversion is an object, which type is the same as the type specified by the type_name. The type of the expression must be known independently from the context. Moreover, the expression cannot be an aggregate, an allocator, the literal null, or a string literal.
The type_name must be the name of an Integer, Floating or Array-type.
When a floating-point number is converted into an Integer, the result is rounded to the nearest Integer.
Type conversions and conversion functions are different things. Type conversions are only defined implicitly for closely related types. For other types, you must write explicit conversion functions.
signal SInt: integer; signal SReal: real; ... SReal <= real(SInt) * 4.0;