EASE: Block diagram editor

The block diagram editor allows you to easily decompose your system into functional blocks. It is up to the designer how detailed you want to make the decomposition. Any block can contain a:

  • Component/instance
  • Generate statement (both for and if)
  • Block statement
  • Process/always statement
  • Concurrent text block
The contents of a block can be implemented using one of the four available editors. The block diagram editor allows you to graphically represent VHDL processes or Verilog always statements. This approach visualizes the data flow inside a single diagram.

The editor supports the use of generics/parameters (both in the interface definition and in the diagrams), complex port maps, (VHDL) records, etc.

EASE Block Diagram Editor
View generated Verilog

Browsers State diagram editor

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