Altium Designer - IO Checker extension

IO Checker is the best tool to exchange data (and verify consistency) between FPGA design and schematic capture.

HDL Works has developed an Altium Designer extension to form a bride between the schematic capture design and IO Checker. The extension allows you to:

  1. Export the schematic netlist to IO Checker and:
    1. Verify the schematics versus a FPGA pin-out file, constraints or user specification.
    2. Create FPGA constraints from the netlist.
    3. Create a Verilog module or a VHDL entity from the netlist.
  2. Add wires (and IO ports) to the parts of an FPGA instantiated on different schematic pages based on the FPGA pin file, design constraints, or a CVS file.

The interface can be used for both initial wiring of components or to update existing schematics because of changes in the pin assignments of the FPGA. For power and ground pins you can add a wire or place a note about the required voltage near the pin. LVDS DIFFPAIR parameters can be added for the LVDS signals and NoDRC attribute to unconnected pins.

Automatically adding wires to components of a large FPGA saves valuable time and guarantees equal signal names in both design environments.

The extension is available for Altium Designer 16, 17, 18 and Nexus. Please contact HDL Works for instructions on how to download and install the Altium Designer extension.
(We are waiting for Altium to review the extension so it can installed

More information on the IO Checker features and its smart verification methodology can be found on the main page.

Altium IO Checker dialog
Altium IO Checker dialog






Altium Designer 18 schematic with one part wired by the IO Checker extension.
Altium Designer schematic wired by the IO Checker extension

Constraints update and generation Supported FPGA vendors and families

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