EASE: Frequently Asked Questions

Introduction

Q:	Where can I get an evaluation license?
A:	If you start EASE without a valid license, the license wizard window will automatically pop-up asking to specify a license file (or license server) or to create a license request. Select the option Create an evaluation license request and press the Finish button. This will take you to the HDL Works website. Fill in the requested information and press the 'Submit' button. With a valid email address and hostid you should receive a license withon half an hour. Or you can send an email to support. NOTE: Every hostid can get an evaluation license only once.
Q:	How can I setup my license environment?
A:	When EASE can not find a license, it will start with a license wizard window. In this wizard select Specify license file/server and press the Next button. On the second page of this wizard specify the license file or license server and press the Finish button. You can also start the license wizard by selecting the Options > License Wizard menu.
Q:	Where should I start after the installation of the software?
A:	If you are a new user we recommend you to follow a tutorial included in the installation package. There is a tutorial for VHDL and for Verilog users.
Q:	Where can I find the tutorials?
A:	After starting the tool choose the Help menu. The files are also available from the installation directory.
Q:	Where can I find the user documentation?
A:	After starting the tool choose the Help menu. The file is also available from the installation directory.

General

Q:	Can I share my design database between different OS?
A:	Yes, you can share your design database between different OS.
Q:	How can I re-use my existing design?
A:	You can import your existing HDL and convert it to graphical diagrams. Choose the File > Import > Import HDL menu.
Q:	How can I configure EASE to use my favorite text-editor?
A:	Choose the Options > User Options menu. Switch to the page HDL > Editor, clear the option Built-in Scriptum editor and browse to your favorite text-editor.
Q:	Does EASE support mixed VHDL and Verilog for a single design?
A:	Yes, you can create a mixed VHDL and Verilog design in EASE.
Q:	How do I change the default startup language?
A:	Choose the Options > User Options menu. Select the page HDL and change the default startup language.
Q:	I do not want to see the verification notes. Can I disable them?
A:	Yes, you can do this in the Options > User Options menu. Switch to the page HDL > Verification and select the check box Disable notes.

Block Diagram Editor

Q:	I have deleted an entity/module, but it is still present in the browser.
A:	You have to use the purge command to really remove an entity/module from your design. Click on the appropriate entity/module in the design browser and select from the pop-up menu Purge.
Q:	How do I instantiate an existing entity/module?
A:	Choose the Diagram > Instantiate menu and select the entity/module you want to instantiate. You can also draw a new component and give it the same name as your existing component. It will now automatically insert the existing component.
Q:	How can I change the diagram contents (e.g. from block to HDL)?
A:	Choose from the component pop-up menu Architecture > Properties and change Contents
Q:	How do I declare a constant?
A:	Select the Add included text button. Select in the pop-up window the text type and declare the constant.
Q:	How do I add a new architecture to an existing module?
A:	Choose from the component pop-up menu Entity > Add Architecture.
Q:	How do I bind the new architecture?
A:	Select Bind from the pop-up menu in the design browser.
Q:	How do I create a configuration?
A:	Select the architecture for which you want to create the configuration in the design browser and select Create configuration from the pop-up menu.
Q:	I would like to change the architecture name, how do I do this?
A:	You can change the default architecture name in the Options > User Options menu. Switch to page HDL > Default Names. For a specific architecture choose from the component pop-up menu Architecture > Properties and change the Name field.
Q:	How do I create a Verilog module in a VHDL design?
A:	Create the module and choose from the component pop-up menu Entity > Properties. Change the HDL type into Verilog.
Q:	How do I create a VHDL entity in a Verilog design?
A:	Create the module and choose from the component pop-up menu Module > Properties. Change the HDL type into VHDL.
Q:	How can I instantiate my IP core?
A:	You can create an external component or you can import HDL code (File > Import > Import HDL); instantiate the component and select Entity > Properties from the component pop-up menu. Select the check box External generated.

FSM Diagram Editor

Q:	How do I specify a default action?
A:	Select the Diagram > Action labels menu. In the window, create a new label, apply the HDL code for this label and select the check box States or Conditions in the section Default on:.
Q:	How do I change the state machine options?
A:	You can change the state machine options in the Diagram > Properties menu. You must be in the statediagram to change this options.
Q:	How do I declare a concurrent statement in a state machine architecture?
A:	Select the button Add included text. Select in the pop-up window the text type Concurrent Statements and enter the statement(s) in the text field.
Q:	How can I change the priority of a transition?
A:	Change the priority in the window Edit Transition by selecting Properties from the transition pop-up menu.
Q:	I get an error 'Clock port flag not found.'. I have an input port Clk on the diagram, so what is wrong?
A:	You have to specify this port as a clock port. Choose Diagram > Properties and switch to page Clock Behaviour. Select the clock from the Signal list in the Clock edge section.
Q:	Can I create multiple state machine processes within one architecture?
A:	Yes, you can specify a suffix to distinguish between names of state machine processes. Choose Diagram > Properties, switch to page Name Space, and specify a suffix in HDL naming convention.

HDL Generation

Q:	How do I change the default output directory?
A:	You can change this by selecting the library in the design browser. Choose Properties from the pop-up menu, switch to page HDL Settings and change the output directory.
Q:	How do I change the default output file?
A:	You can change this by selecting the library in the design browser. Choose Properties from the pop-up menu, switch to page HDL Settings and change the output file.
Q:	How can I select to generate all in one file?
A:	Select the File > Properties menu and switch to page HDL > Files.
Q:	How can I select to generate all diagrams in separate files?
A:	Select the File > Properties menu and and switch to page HDL > Files.
Q:	Where can I find the generated files?
A:	The default output directory <library name>.hdl is located in the Ease project directory <project>.ews.
Q:	Ease does not generate VHDL93 compliant code.
A:	You can change this by choosing the File > Properties menu. Switch to page HDL > VHDL and select the check box Generate VHDL93 compliant code.

Version Management

Q:	How do I configure the version management tool?
A:	Choose the Options > User Options menu. Switch to page Versioning and enable Subversion. After configuration you can create a project in the File > Subversion menu.
Q:	Do I need a separate license for version management?
A:	Version management is part of Ease TE. It has a separate feature line, versioning, in the license file.
Q:	Do I need a license for Subversion?
A:	Subversion is an open-source revision control system (https://subversion.apache.org). Which aims to be a compelling replacement for CVS.
Q:	How can I see a (part of) design is checked-in?
A:	Checked-in entities/modules are colored blue in the design browser. Checked-out entities/modules are colored black. In the diagrams checked-in entities/modules have a shading.
Q:	The button bar is not visible in Ease what happens?
A:	The button bar is not visible if the diagram is checked-in. If you check-out this diagram the button bar will become visible.
Q:	What is a tag?
A:	A tag is a symbolic name to a certain revision of a file. A more common use is to tag all the files that constitute a logical unit with the same tag at strategic points in the development life-cycle, such as when a release is made.
Q:	What is a branch?
A:	The version tree of a specific object may form a simple linear sequence. Occasionalyy it may be useful to define additional branches, e.g. for bug fixes or experiments. When using Subversion, Ease will always perform all versioning actions on the leaf cell of the currently selected branch for all objects managed by Ease. At this moment Ease does not support the merge of branches.
Q:	My colleague changed his module, but I do not see his changes.
A:	You have to update your workspace before his changes become visible in your design. You have to check-in your whole project and choose File > Subversion > Update workspace.