The Lint tool analyzes your VHDL or Verilog code and reports potential problems which are not found by the compilers. It offers you a simple but fast method to improve the quality of the HDL code. It is intended to find all kinds of language constructs that are formally correct but probably not intended. Examples are signals that are defined but never used; signals that are on the sensitivity list of a process but not used inside the process; etc. You can run the Lint tool on the whole project or on packages, entities or modules separately. The results are displayed in the Lint tab of the Console Window. You can double click on a message to directly navigate to the source file and inspect the HDL code.
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