EASE: External HDL

Core gen module and Unisim library

External HDL files like IP, legacy code, Matlab code and FPGA generated models (like Xilinx Coregen or Platform Studio) can be easily integrated in your project as external objects. EASE will create symbols and component declarations for instantiated modules, but keeps the files as the original HDL source files. You will be notified when newer files are present and symbols can be easily updated to the latest version.

Symbol libraries for FPGA primitives (like Xilinx Unisim) can be created on the fly from vendor VHDL or Verilog descriptions. They are translated into a load-on-demand library to improve performance.

Existing HDL that contains hierarchy can also be translated into block diagrams, which are then the base for further development. Please bare in mind that schematic generation is never as good as hand-crafted diagrams.

Scriptum Verification and Linting

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