Before VHDL or Verilog is generated EASE verifies the design for inconsistencies and syntax errors. All notes, warnings and errors are reported in the verification pane. The messages are hot-linked to the corresponding editor to quickly navigate to the offending code. Linting is an additional verification effort to find potential design problems (like range mismatches in assignments of vectors, or read-only signals). The lint rules are a combination of the DO-254 'Best Practice Design Rule Set's and HDL Works defined rules. The severity level (note, warning or error) can be set for each rule separately.
Please contact HDL Works to receive the full list of lint checks.
You can define name conventions at both corporate and user level and apply a configuration to any of your projects. The names of objects like entities, ports, generics, modules, parameters, constants, components can be verified to comply using a regular expression.
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